NetNews Offline 2/NetNews Offline Volume 2.iso/news/comp/sys/amiga/programmer/6790

Text File | 1996-08-05 | 4.9 KB | 104 lines

Newsgroups: comp.sys.amiga.programmer
Path: netnews.upenn.edu!dsinc!scala!news
From: [e-mail] (Dave Haynie)
Subject: Re: CHIP RAM speed test resul
Sender: [e-mail] (Usenet administrator)
Message-ID: <[e-mail]>
Date: Tue, 2 Apr 1996 23:45:28 GMT
Reply-To: [e-mail] (Dave Haynie)
References: <4j6jv0$[e-mail]> <[e-mail]>
Nntp-Posting-Host: gator
Organization: Scala Computer Television, US Research Center

In <[e-mail]>, [e-mail] (Fabio Bizzetti) writes:

>As far as I recall my A1200 chipram is 80ns; while it's exploited as if it was
>only 140ns. The rest of ns is wasted because Alice holds control of everything,
>and Alice is slower than the CPU.

You don't understand dynamic RAM. The 80ns rating on a DRAM is the row
address access time. That's usually (depending on the part and the
memory controller), the fastest that data can be accessed from that
part. However, DRAM also has a row address precharge time, which is
usually about 60-80% of the access time. So while you can access a
word in 80ns from the start of the memory cycle, you can't
continuously run random access cycles any faster than around 140ns,
for an 80ns part.

>Since you didn't get what I meant last time, I'll try to explain my thought
>better: if you put 10ns ram in your 68030 board, it doesn't mean that it will
>be exploited as 10ns. It will be exploited as your ram controller allows, 60ns
>or 70ns commonly.

Which is 100ns-120ns cycle times, commonly, for those memory speeds.

>Well, the chips inside my A1200 ("chipram") are much faster than
>they're supposed to be, but Alice brakes the CPU to gain from this
>speed because in fact Alice is chipram's controller.

Not at all. The 80ns parts on the chip bus are exactly as fast as
they're supposed to be. The constraint on speed is not the normal
access time, but the timing for Alice's burst cycles. For video fetch,
Alice runs 64-bits to Lisa every 280ns. The burst cycle timing is
fairly critical, so 100ns parts would not work here.

>>It is clear that you can do better than current 7MHz chip RAM but
>>that's because RAM is faster nowadays.

>It would be sufficient to modify the interface   CPU <->chipram<-> Alice.

If Alice were designed in a modern process, and you ran the actual
chip bus timing from a 28MHz or 56MHz basis, rather than the 14MHz at
present, you could probably run four cycle bursts to Chip RAM in the
280ns window. Maybe CPU bursts too, though there's another problem
with memory access, and that's one of matching the cycle to the
CPU. It does you no good if you have data ready when the CPU can't
take it. The chip bus is a synchronous bus, and if you were to burst
four words out of it for a CPU cycle, you would either need a CPU that
perfectly aligned with the chip bus timing, or you would need a FIFO
device to store the fetched data for when CPU could take it.

>Maybe the "ram controller" that you wish (to multiplex data) would be more
>expensive than 2Mb of real dual access ram, this is to be examinated.

Real dual-ported random access memory is exotic. You usually get it in
hundred-byte chips, generally used for contention-free mailboxes in
high performance multiprocessing systems. Video RAM (VRAM) is a
special purpose dual ported RAM, and it's commonly used in graphics
systems to get the video fetch activity decoupled from the "chip
bus". The AAA system supported VRAM, but it's a rather tricky thing to
support, since the video access portion is serial, not random
access. The AAA chips used a double line-buffer scheme to get around
this, but it's not a real cheap solution. More primitive graphics
systems can limit where displays live in order to simplify the
requirements for VRAM.

However, VRAM is expensive, since it's roughly 50% larger per cell
than DRAM. There's no inherent advantage to dual porting over other
methods. The main goal in making a faster graphics system is to speed
up the aggregrate bandwidth of the system. Dual porting can double (or
more like triple) a memory's bandwidth. But if I speed memory access
other ways, like increasing the bus size, I can get the same
advantages by time multiplexing the bus. There's nothing inherently
wrong with the way the Amiga does it, it's just dealing with
technology that began life in the mid 80s.

>> We already have "dual port RAM", just the multiplexing is done outside the
>> chip.
>
>This is the problem: it's performed by the 7Mhz (bus clock) of Alice.

Alice has a 14MHz bus clock.

>Just think, 24Mb/sec

Oh by the way, "24Mb/sec" means "24 megabits per second". I think you
mean 24MB/s in all your talk here...

Dave Haynie          | ex-Commodore Engineering |   for DiskSalv 3 &
Sr. Systems Engineer |  Hardwired Media Company | "The Deathbed Vigil"
Scala Inc., US R&D   |    Ki No Kawa Aikido     |     [e-mail]

         "Feeling ... Pretty ... Psyched" -R.E.M.